| Implementing High Availability Memory With a Duplication Cache | Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan |
| Low-Power, High-Performance Analog Neural Branch Prediction | Renée St. Amant, Daniel A. Jiménez, Doug Burger |
| Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach | Ramazan Bitirgen, Engin Ipek, José F. Martínez |
| Power Reduction of CMP Communication Networks via RF-Interconnects | M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam |
| Hybrid Analytical Modeling of Pending Cache Hits, Data Prefetching, and MSHRs | Xi E. Chen, Tor M. Aamodt |
| Shapeshifter: Dynamically Changing Pipeline Width and Speed to Address Process Variations | Eric Chun, Zeshan Chishti, T. N. Vijaykumar |
| Online Design Bug Detection: RTL Analysis, Flexible Mechanisms, and Evaluation | Kypros Constantinides, Onur Mutlu, Todd M. Austin |
| Evaluating the Effects of Cache Redundancy on Profit | Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary |
| Reconfigurable Energy Efficient Near Threshold Cache Architectures | Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztián Flautner |
| Temporal Instruction Fetch Streaming | Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos |
| NBTI Tolerant Microarchitecture Design in the Presence of Process Variation | Xin Fu, Tao Li, José A. B. Fortes |
| A Performance-Correctness Explicitly-Decoupled Architecture | Alok Garg, Michael C. Huang |
| A Distributed Processor State Management Architecture for Large-Window Processors | Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero |
| Toward a Multicore Architecture for Real-Time Ray-Tracing | Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary K. Vernon, William R. Mark |
| Testudo: Heavyweight Security Analysis via Statistical Sampling | Joseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie |
| The StageNet Fabric for Constructing Resilient Multicore Systems | Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke |
| Virtual Tree Coherence: Leveraging Regions and In-Network Multicast Trees for Scalable Cache Coherence | Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti |
| Adaptive Data Compression for High-Performance Low-Power On-Chip Networks | Yuho Jin, Ki Hwan Yum, Eun Jung Kim |
| Token Flow Control | Amit Kumar, Li-Shiuan Peh, Niraj K. Jha |
| CPR: Composable Performance Regression for Scalable Multiprocessor Models | Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks |
| Prefetch-Aware DRAM Controllers | Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt |
| Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efficiency | Haiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger |
| Tradeoffs in Designing Accelerator Architectures for Visual Computing | Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel |
| Token Tenure: PATCHing Token Counting Using Directory-Based Cache Coherence | Arun Raghavan, Colin Blundell, Milo M. K. Martin |
| Dependence-Aware Transactional Memory for Increased Concurrency | Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel |
| Strategies for Mapping Dataflow Blocks to Distributed Hardware | Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley |
| Efficient Unicast and Multicast Support for CMPs | Samuel Rodrigo, José Flich, José Duato, Mark Hummel |
| EVAL: Utilizing Processors With Variation-Induced Timing Errors | Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas |
| Verification of Chip Multiprocessor Memory Systems Using a Relaxed Scoreboard | Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz |
| Power to the People: Leveraging Human Physiological Traits to Control Microprocessor Frequency | Alex Shye, Yan Pan, Benjamin Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick |
| Reducing the Harmful Effects of Last-Level Cache Polluters With an OS-Level, Software-Only Pollute Buffer | Livio Soares, David K. Tam, Michael Stumm |
| Copy or Discard Execution Model for Speculative Parallelization on Multicores | Chen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta |
| A Small Cache of Large Ranges: Hardware Methods for Efficiently Searching, Storing, and Updating Big Dataflow Tags | Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood |
| Facelift: Hiding and Slowing Down Aging in Multicores | Abhishek Tiwari, Josep Torrellas |
| SHARK: Architectural Support for Autonomic Protection Against Stealth by Rootkit Exploits | Vikas R. Vasisht, Hsien-Hsin S. Lee |
| A Novel Cache Architecture With Enhanced Performance and Security | Zhenghong Wang, Ruby B. Lee |
| From SODA to Scotch: The Evolution of a Wireless Baseband Processor | Mark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner |
| Notary: Hardware Techniques to Enhance Signatures | Luke Yen, Stark C. Draper, Mark D. Hill |
| Microarchitecture Soft Error Vulnerability Characterization and Mitigation Under 3D Integration Technology | Wangyuan Zhang, Tao Li |
| Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency | Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu |
