ACM SIGMICRO

List of Eligible Papers for the 2024 Award

View the 2024 call for nominations.

MICRO 2003

Paper Title	Authors
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power	Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
TLC: Transmission Line Caches	Bradford M. Beckmann, David A. Wood
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures	Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches	Se-Hyun Yang, Babak Falsafi
Power-Driven Design of Router Microarchitectures in On-Chip Networks	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
Optimum Power/Performance Pipeline Depth	Allan Hartstein, Thomas R. Puzak
Processor Acceleration Through Automated Instruction Set Customization	Nathan Clark, Hongtao Zhong, Scott A. Mahlke
The Reconfigurable Streaming Vector Processor (RSVPTM)	Silviu M. S. A. Chiricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael A. Schuette, Ali Saidi
Scaling and Characterizing Database Workloads: Bridging the Gap Between Research and Practice	Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen
Generational Cache Management of Code Traces in Dynamic Optimization Systems	Kim M. Hazelwood, Michael D. Smith
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System	Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen
IA-32 Execution Layer: A Two-Phase Dynamic Translator Designed to Support IA-32 Applications on Itanium-Based Systems	Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach
LLVA: A Low-level Virtual Instruction Set Architecture	Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke
Comparing Program Phase Detection Techniques	Ashutosh S. Dhodapkar, James E. Smith
Using Interaction Costs for Microarchitectural Bottleneck Analysis	Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn
Fast Path-Based Neural Branch Prediction	Daniel A. Jiménez
Hardware Support for Control Transfers in Code Caches	Ho-Seop Kim, James E. Smith
Exploiting Value Locality in Physical Register Files	Saisanthosh Balakrishnan, Gurindar S. Sohi
Macro-Op Scheduling: Relaxing Scheduling Loop Constraints	Ilhyun Kim, Mikko H. Lipasti
WaveScalar	Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin
Universal Mechanisms for Data-Parallel Architectures	Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors	Enric Gibert, F. Jesús Sánchez, Antonio González
Instruction Replication for Clustered Microarchitectures	Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
Efficient Memory Integrity Verification and Encryption for Secure Processors	G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas
Fast Secure Processor for Inhibiting Software Piracy and Tampering	Jun Yang, Youtao Zhang, Lan Gao
IPStash: A Power-Efficient Memory Architecture for IP-Lookup	Stefanos Kaxiras, Georgios Keramidas
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers	Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero
Beating In-Order Stalls With "Flea-Flicker" Two-Pass Pipelining	Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu
Scalable Hardware Memory Disambiguation for High ILP Processors	Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler
Reducing Design Complexity of the Load/Store Queue	Il Park, Chong-liang Ooi, T. N. Vijaykumar
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors	Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan

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MICRO 2004

Paper Title	Authors
The Fuzzy Correlation Between Code and Performance Predictability	Murali Annavaram, Ryan N. Rakvic, Marzia Polito, Jean-Yves Bouguet, Richard A. Hankins, Bob Davies
Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery	David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt
Cache Refill/Access Decoupling for Vector Machines	Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic
Managing Wire Delay in Large Chip-Multiprocessor Caches	Bradford M. Beckmann, David A. Wood
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth	Anne Bracy, Prashant Prahlad, Amir Roth
Automatic Synthesis of High-Speed Processor Simulators	Martin Burtscher, Ilya Ganusov
Dynamically Controlled Resource Allocation in SMT Processors	Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization	Nathan Clark, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke, Krisztián Flautner
Control Flow Optimization Via Dynamic Reconvergence Prediction	Jamison D. Collins, Dean M. Tullsen, Hong Wang
Minos: Control Data Attack Prevention Orthogonal to Memory Model	Jedidiah R. Crandall, Frederic T. Chong
A Hardware-Software Platform for Intrusion Prevention	Milenko Drinic, Darko Kirovski
Dynamically Trading Frequency for Complexity in a GALS Microprocessor	Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure	Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev
Compiler Optimizations for Transaction Processing Workloads on Itanium Linux Systems	Gerolf Hoflehner, Knud Kirkegaard, Rod Skinner, Daniel M. Lavery, Yong-Fong Lee, Wei Li
Adaptive History-Based Memory Schedulers	Ibrahim Hur, Calvin Lin
Conjoined-Core Chip Multiprocessing	Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
A Case for Clumsy Packet Processors	Arindam Mallik, Gokhan Memik
Pinpointing Representative Portions of Large Intel Itanium Programs With Dynamic Instrumentation	Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms	Daniel Gracia Pérez, Gilles Mouchard, Olivier Temam
Memory Controller Optimizations for Web Servers	Scott Rixner
Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication	Peter G. Sassone, D. Scott Wills
Thermal Modeling, Characterization and Management of On-Chip Networks	Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha
Optimal Superblock Scheduling Using Enumeration	Ghassan Shobaki, Kent D. Wilken
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures	Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi
Hardware and Binary Modification Support for Code Pointer Protection From Buffer Overflow	Nathan Tuck, Brad Calder, George Varghese
Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy	Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
RIFLE: An Architectural Framework for User-Centric Information-Flow Security	Neil Vachharajani, Matthew J. Bridges, Jonathan Chang, Ram Rangan, Guilherme Ottoni, Jason A. Blome, George A. Reis, Manish Vachharajani, David I. August
Whole Execution Traces	Xiangyu Zhang, Rajiv Gupta
AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants	Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas

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MICRO 2005

Paper Title	Authors
How to Fake 1000 Registers	David W. Oehmke, Nathan L. Binkert, Trevor Mudge, Steven K. Reinhardt
Reducing Instruction Fetch Cost by Packing Instructions Into Register Windows	Stephen Hines, Gary Tyson, David Whalley
Efficient Use of Invisible Registers in Thumb Code	Arvind Krishnaswamy, Rajiv Gupta
Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution	Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt
A Criticality Analysis of Clustering in Superscalar Processors	Pierre Salverda, Craig Zilles
Incremental Commit Groups for Non-Atomic Trace Processing	Matt T. Yourst, Kanad Ghose
Pinot: Speculative Multi-Threading Processor Architecture Exploiting Parallelism Over a Wide Range of Granularities	Taku Ohsawa, Masamichi Takagi, Shoji Kawahara, Satoshi Matsushita
Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor	Jiwei Lu, Abhinav Das, Wei-Chung Hsu, Khoa Nguyen, Santosh G. Abraham
Automatic Thread Extraction With Decoupled Software Pipelining	Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August
Exploiting Vector Parallelism in Software Pipelined Loops	Samuel Larsen, Rodric Rabbah, Saman Amarasinghe
Continuous Path and Edge Profiling	Michael D. Bond, Kathryn S. McKinley
Improving Region Selection in Dynamic Optimization Systems	David Hiniker, Kim Hazelwood, Michael D. Smith
Scalable Store-Load Forwarding via Store Queue Index Prediction	Tingting Sha, Milo M. K. Martin, Amir Roth
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding	Sam S. Stone, Kevin M. Woley, Matthew I. Frank
Store Memory-Level Parallelism Optimizations for Commercial Applications	Yuan Chou, Lawrence Spracklen, Santosh G. Abraham
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors	Fred A. Bower, Daniel J. Sorin, Sule Ozev
μComplexity: Estimating Processor Design Effort	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System	Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott Mahlke
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns	Onur Mutlu, Hyesoon Kim, Yale N. Patt
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors	Meyrem Kyrman, Nevin Kyrman, José F. Martínez
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing	Smruti R. Sarangi, Wei Liu, Josep Torrellas, Yuanyuan Zhou
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance	Qiang Wu, Margaret Martonosi, Douglas W. Clark, V. J. Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
Thermal Management of On-Chip Caches Through Power Density Minimization	Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea Ismail
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines	Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar
A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation	Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Frederic T. Chong, Isaac L. Chuang
"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense	Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu
The TM3270 Media-Processor	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans van Antwerpen
Stream Programming on General-Purpose Processors	Jayanth Gummaraju, Mendel Rosenblum
Shader Performance Analysis on a Modern GPU Architecture	Victor Moya, Carlos Gonzalez, Jordi Roca, Agustin Fernandez, Roger Espasa

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MICRO 2006

Paper Title	Authors
Virtually Pipelined Network Memory	Banit Agrawal, Timothy Sherwood
ASR: Adaptive Selective Replication for CMP Caches	Bradford M. Beckmann, Michael R. Marty, David A. Wood
Die Stacking (3D) Microarchitecture	Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb
Serialization-Aware Mini-Graphs: Performance With Fewer Resources	Anne Bracy, Amir Roth
DMDC: Delayed Memory Dependence Checking Through Age-Based Filtering	Fernando Castro, Luis Piñuel, Daniel Chaver, Manuel Prieto, Michael C. Huang, Francisco Tirado
Managing Distributed, Shared L2 Caches Through OS-Level Page Allocation	Sangyeun Cho, Lei Jin
In-Network Cache Coherence	Noel Eisley, Li-Shiuan Peh, Li Shang
Fairness and Throughput in Switch on Event Multithreading	Ron Gabor, Shlomo Weiss, Avi Mendelson
Data-Dependency Graph Transformations for Superblock Scheduling	Mark Heffernan, Kent D. Wilken, Ghassan Shobaki
Memory Prefetching Using Adaptive Stream Detection	Ibrahim Hur, Calvin Lin
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget	Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose, Margaret Martonosi
Live, Runtime Phase Monitoring and Prediction on Real Systems With Application to Dynamic Power Management	Canturk Isci, Gilberto Contreras, Margaret Martonosi
A Predictive Performance Model for Superscalar Processors	P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil
Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt
Leveraging Optical Technology in Future Bus-Based Chip Multiprocessors	Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units	Xiaoyao Liang, David M. Brooks
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection	Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas
Merging Head and Tail Duplication for Convergent Hyperblock Formation	Bertrand A. Maher, Aaron Smith, Doug Burger, Kathryn S. McKinley
Coherence Ordering for Ring-Based Chip Multiprocessors	Michael R. Marty, Mark D. Hill
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design	Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee
Fair Queuing Memory Systems	Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers	Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das
Yield-Aware Cache Architectures	Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs	Pierre Palatin, Yves Lhuillier, Olivier Temam
LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks	Feng Qin, Cheng Wang, Zhenmin Li, Ho-Seop Kim, Yuanyuan Zhou, Youfeng Wu
Support for High-Frequency Streaming in CMPs	Ram Rangan, Neil Vachharajani, Adam Stoler, Guilherme Ottoni, David I. August, George Z. N. Cai
Architectural Support for Software Transactional Memory	Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson
Exploiting Fine-Grained Data Parallelism With Chip Multiprocessors and Fast Barriers	Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger
Phoenix: Detecting and Recovering From Permanent Processor Design Bugs With Programmable Hardware	Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas
NoSQ: Store-Load Communication Without a Store Queue	Tingting Sha, Milo M. K. Martin, Amir Roth
Authentication Control Point and Its Implications for Secure Processor Design	Weidong Shi, Hsien-Hsin S. Lee
Dataflow Predication	Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley
Reunion: Complexity-Effective Multicore Redundancy	Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe
Fire-and-Forget: Load/Store Scheduling With No Store Queue at All	Samantika Subramaniam, Gabriel H. Loh
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads	Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh
Scalable Cache Miss Handling for High Memory-Level Parallelism	James Tuck, Luis Ceze, Josep Torrellas
Molecular Caches: A Caching Structure for Dynamic Creation of Application-Specific Heterogeneous Cache Regions	Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units	Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry
Memory Protection Through Dynamic Access Control	Kun Zhang, Tao Zhang, Santosh Pande
Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection	Xiaotong Zhuang, Tao Zhang, Santosh Pande

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MICRO 2007

Paper Title	Authors
Penelope: The NBTI-Aware Processor	Jaume Abella, Xavier Vera, Antonio González
Scavenger: A New Last Level Cache Architecture With Global Block Priority	Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
Self-Calibrating Online Wearout Detection	Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke
Revisiting the Sequential Programming Model for Multi-Core	Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas B. Jablin, David I. August
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators	Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat
Informed Microarchitecture Design Space Exploration Using Workload Dynamics	Chang-Burm Cho, Wangyuan Zhang, Tao Li
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications	Yuan Chou
Data Access Partitioning for Fine-Grain Parallelism on Multicore Architectures	Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation	Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach	Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow	Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs	Mrinmoy Ghosh, Hsien-Hsin S. Lee
A Framework for Providing Quality of Service in Chip Multi-Processors	Fei Guo, Yan Solihin, Li Zhao, Ravishankar R. Iyer
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache	Stephen Hines, David B. Whalley, Gary S. Tyson
Flattened Butterfly Topology for On-Chip Networks	John Kim, James D. Balfour, William J. Dally
Multi-Bit Error Tolerant Caches Using Two-Dimensional Error Coding	Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe
Composable Lightweight Processors	Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler
Impact of Cache Coherence Protocols on the Processing of Network Traffic	Amit Kumar, Ram Huggahalli
Process Variation Tolerant 3T1D-Based Cache Architectures	Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks
Leveraging 3D Technology for Improved Reliability	Niti Madan, Rajeev Balasubramonian
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores	Albert Meixner, Michael E. Bauer, Daniel J. Sorin
Effective Optimistic-Checker Tandem Core Design Through Architectural Pruning	Francisco J. Mesa-Martinez, Jose Renau
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0	Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors	Onur Mutlu, Thomas Moscibroda
Time Interpolation: So Many Metrics, So Few Registers	Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan
Global Multi-Threaded Instruction Scheduling	Guilherme Ottoni, David I. August
Emulating Optimal Replacement With a Shepherd Cache	Kaushik Rajan, Ramaswamy Govindarajan
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly	Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin
Implementing Signatures for Transactional Memory	Daniel Sánchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors	Karin Strauss, Xiaowei Shen, Josep Torrellas
Mitigating Parameter Variation With Dynamic Fine-Grain Body Biasing	Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs	William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe
Optimal Versus Heuristic Global Code Scheduling	Sebastian Winkel
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration	Thomas Y. Yeh, Petros Faloutsos, Milos D. Ercegovac, Sanjay J. Patel, Glenn Reinman
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy	Jason Zebchuk, Elham Safi, Andreas Moshovos

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